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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GITS_CREADR, ITS Read Register</h1><p>The GITS_CREADR characteristics are:</p><h2>Purpose</h2>
        <p>Specifies the offset from <a href="ext-gits_cbaser.html">GITS_CBASER</a> where the ITS reads the next ITS command.</p>
      <h2>Configuration</h2>
        <p>This register is cleared to 0 when a value is written to <a href="ext-gits_cbaser.html">GITS_CBASER</a>.</p>

      
        <p>Bits [63:32] and bits [31:0] are accessible separately.</p>
      <h2>Attributes</h2>
        <p>GITS_CREADR is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_20">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="12"><a href="#fieldset_0-63_20">RES0</a></td><td class="lr" colspan="15"><a href="#fieldset_0-19_5">Offset</a></td><td class="lr" colspan="4"><a href="#fieldset_0-4_1">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">Stalled</a></td></tr></tbody></table><h4 id="fieldset_0-63_20">Bits [63:20]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-19_5">Offset, bits [19:5]</h4><div class="field">
      <p>Bits [19:5] of the offset from <a href="ext-gits_cbaser.html">GITS_CBASER</a>. Bits [4:0] of the offset are zero.</p>
    </div><h4 id="fieldset_0-4_1">Bits [4:1]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-0_0">Stalled, bit [0]</h4><div class="field">
      <p>Reports whether the processing of commands is stalled because of a command error.</p>
    <table class="valuetable"><tr><th>Stalled</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>ITS command queue is not stalled because of a command error.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>ITS command queue is stalled because of a command error.</p>
        </td></tr></table></div><div class="text_after_fields">
    <p>For more information, see <span class="xref">'The ITS command interface' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069)</span>.</p>
  </div><h2>Accessing GITS_CREADR</h2><h4>GITS_CREADR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC ITS control</td><td><span class="hexnumber">0x0090</span></td><td>GITS_CREADR</td></tr></table><p>Accesses on this interface are <span class="access_level">RO</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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